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preliminary data sheet ? 1997, 1999 the m pd78f0988 is a member of the m pd780988 subseries of the 78k/0 series that substitute flash memory for the internal rom of the m pd780988. flash memory can be written or erased electrically without having to remove it from board. therefore, the m pd78f0988 is best suited for evaluation in system development, small-scale production, or systems likely to be upgraded frequently. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m pd780988 subseries users manual: u13029e 78k/0 series instructions users manual: u12326e features ? pin-compatible with mask rom version (except v pp pin) ? flash memory: 60 kbytes note 1 ? internal high-speed ram: 1024 bytes ? internal expansion ram: 1024 bytes note 2 ? operable in the same supply voltage range as the mask rom version (v dd = 4.0 to 5.5 v) notes 1. the capacity of the flash memory can be changed with the internal memory size switching register (ims). 2. the capacity of the internal expansion ram can be changed with the internal expansion ram size switching register (ixs). remark for the differences between the flash memory versions and the mask rom versions, refer to 1. differences between m pd78f0988 and mask rom versions. ordering information part number package m pd78f0988cw 64-pin plastic shrink dip (750 mil) m pd78f0988gc-ab8 64-pin plastic qfp (14 14 mm) mos integrated circuit 8-bit single-chip microcontroller m pd78f0988 document no. u12805ej1v0ds00 (1st edition) date published june 1999 n cp(k) printed in japan the mark shows major revised points. the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 m pd78f0988 preliminary data sheet u12805ej1v0ds00 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. pd780955 pd78083 pd78044f 80 -pin basic subseries for fip driving, total display output: 34 pd78044h 80 -pin pd78044f with n-ch open-drain i/o, total display output: 34 pd780232 80 -pin for panel control and on-chip fip c/d, total display output: 53 pd780034a pd780024a pd780024ay pd78014h pd78018f 64 -pin 64 -pin 64 -pin 64 -pin pd780024a with enhanced a/d converter pd78018f with enhanced serial i/o pd78018f with reduced emi noise basic subseries for control pd78018fy pd780034ay pd780078 64 -pin pd780034a with timer and enhanced serial i/o pd780078y pd780208 pd780228 pd780308 pd78064b pd78064 pd780308y pd78064y 42/44 -pin 100 -pin 100 -pin 100 -pin 100 -pin 100 -pin for lcd driving for fip tm driving 78k/0 series on-chip uart and capable of low-voltage (1.8 v) operation pd78044f with enhanced i/o and fip c/d, total display output: 53 pd78044h with enhanced i/o and fip c/d, total display output: 48 pd780988 64 -pin for inverter control pd780841 80 -pin call id supporting on-chip inverter control circuit and uart, emi noise reduced product on-chip call id function and simple dtmf, emi noise reduced product pd78064 with enhanced sio and expanded rom and ram pd78064 with reduced emi noise basic subseries for lcd driving and on-chip uart 80 -pin on-chip j1850 (class2) controller specialized in dcan controller pd78098b pd780973 pd780824 80 -pin 80 -pin 80 -pin 80 -pin for meter control bus interface supporting pd78054 with iebus tm controller, emi noise reduced product on-chip dcan/iebus controller on-chip controller/driver for automobile meter driving for automobile meter driving and on-chip dcan controller 80 -pin ultra low power consumption and on-chip uart in mass-production under development y subseries products are compatible with i 2 c bus. pd780065 80 -pin pd780024a with expanded ram pd780058 pd78058f pd78054 80 -pin 80 -pin 80 -pin pd78054 with enhanced serial i/o pd78054 with reduced emi noise pd78018f with uart and d/a converter, and enhanced i/o 100 -pin pd78078 pd78070a pd78075b 100 -pin 100 -pin 100 -pin for control pd78054 with timer and enhanced external interface function pd78078 with reduced emi noise rom-less version of the pd78078 pd78078y with enhanced serial i/o and restricted function pd78054y pd78058fy pd780058y pd780018ay pd78070ay pd78078y pd780948 100 -pin on-chip dcan controller pd780958 100 -pin for industrial meter control pd780814 64 -pin pd780833y pd780701y m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m
3 m pd78f0988 preliminary data sheet u12805ej1v0ds00 for m pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch C 2 ch 3 ch (uart: 1 ch) 88 1.8 v ? control m pd78078 48 k to 60 k m pd78070a C 61 2.7 v m pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v m pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780065 40 k to 48 k C 4 ch (uart: 1 ch) 60 2.7 v m pd780078 48 k to 60 k 2 ch C 8 ch 3 ch (uart: 2 ch) 52 1.8 v m pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 m pd780024a 8 ch C m pd78014h 2 ch 53 m pd78018f 8 k to 60 k m pd78083 8 k to 16 k C C 1 ch (uart: 1 ch) 33 C for m pd780988 16 k to 60 k 3 ch note C1 chC8 chC 3 ch (uart: 2 ch) 47 4.0 v ? inverter control for fip m pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C C 2 ch 74 2.7 v C driving m pd780228 48 k to 60 k 3 ch C C 1 ch 72 4.5 v m pd780232 16 k to 24 k 4 ch 2 ch 40 m pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v m pd78044f 16 k to 40 k 2 ch for lcd m pd780308 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C C 3 ch (time-division uart: 1 ch) 57 2.0 v C driving m pd78064b 32 k 2 ch (uart: 1 ch) m pd78064 16 k to 32 k call id m pd780841 24 k to 32 k 2 ch C 1 ch 1 ch 2 ch C C 2 ch (uart: 1 ch) 61 2.7 v C supporting bus m pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch C C 3 ch (uart: 1 ch) 79 4.0 v ? interface m pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v C supporting m pd780814 32 k to 60 k 2 ch 12 ch C 2 ch (uart: 1 ch) 46 4.0 v for meter m pd780958 48 k to 60 k 4 ch 2 ch C 1 ch C C C 2 ch (uart: 1 ch) 69 2.2 v C control m pd780973 24 k to 32 k 3 ch 1 ch 1 ch 5 ch 56 4.5 v m pd780824 32 k to 60 k 59 4.0 v m pd780955 40 k 6 ch C 1 ch 2 ch (uart: 2 ch) 50 2.2 v timer 8-bit 16-bit watch wdt serial interface i/o 8-bit a/d rom capacity external expansion v dd min. value subseries name function 10-bit a/d 8-bit d/a the major functional differences among the subseries are listed below. note 16-bit timer: 2 channels 10-bit timer: 1 channel
4 m pd78f0988 preliminary data sheet u12805ej1v0ds00 overview of functions item function internal flash memory 60 kbytes note 1 memory high-speed ram 1024 bytes expansion ram 1024 bytes note 2 memory space 64 kbytes general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) instruction cycle on-chip instruction execution time variable function 0.24 m s/0.48 m s/0.96 m s/1.9 m s/3.8 m s (@ 8.38-mhz operation with system clock) instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjust, etc. i/o ports total: 47 cmos inputs: 8 cmos i/os: 39 real-time output ports 8 bits 1 or 4 bits 2 6 bits 1 or 4 bits 1 a/d converter 10-bit resolution 8 channels power supply voltage: av dd = 4.0 to 5.5 v serial interface uart mode: 2 channels 3-wire serial i/o mode: 1 channel timer 16 bit timer/event counter: 2 channels 8-bit timer/event counter: 3 channels 10-bit inverter control timer: 1 channel watchdog timer: 1 channel timer output 11 (general-purpose outputs: 5 and inverter control outputs: 6) vectored maskable internal: 16, external: 8 interrupt non-maskable internal: 1 sources software 1 power supply voltage v dd = 4.0 to 5.5 v operating ambient temperature t a = e40 to +85 c package 64-pin plastic shrink dip (750 mil) 64-pin plastic qfp (14 14 mm) notes 1. the capacity of the flash memory can be changed with the internal memory size switching register (ims). 2. the capacity of the internal expansion ram can be changed with the internal expansion ram size switching register (ixs).
5 m pd78f0988 preliminary data sheet u12805ej1v0ds00 pin configuration (top view) 64-pin plastic shrink dip (750 mil) m pd78f0988cw caution in the normal operation mode, connect the v pp pin directly to v ss0 . remark when the m pd78f0988 is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50 p51/sck p52/si p53/so p54/ti000/to00/intp4 p55/ti010/intp5 p56/ti001/to01/intp6 p57/ti011/intp7 v ss0 v dd0 to70 to71 to72 to73 to74 to75 p20/rxd00 p21/txd00 p22/rxd01 p23/txd01 p24/ti50/to50 p25/ti51/to51 p26/ti52/to52 v dd1 p67/astb p66/wait p65/wr p64/rd p37/rtp7 p36/rtp6 p35/rtp5 p34/rtp4 p33/rtp3 p32/rtp2 p31/rtp1 p30/rtp0 p01/intp1 p00/intp0/toff7 v ss1 x1 x2 test p03/intp3/adtrg p02/intp2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
6 m pd78f0988 preliminary data sheet u12805ej1v0ds00 64-pin plastic qfp (14 14 mm) m pd78f0988gc-ab8 caution in the normal operation mode, connect the v pp pin directly to v ss0 . remark when the m pd78f0988 is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p50 p51/sck p52/si p53/so p54/ti000/to00/intp4 p55/ti010/intp5 p56/ti001/to01/intp6 p57/ti011/intp7 v ss0 v dd0 to70 to71 to72 to73 to74 to75 p33/rtp3 p32/rtp2 p31/rtp1 p30/rtp0 p01/intp1 p00/intp0/toff7 v ss1 x1 x2 test p03/intp3/adtrg p02/intp2 reset av dd av ref p10/ani0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p20/rxd00 p21/txd00 p22/rxd01 p23/txd01 p24/ti50/to50 p25/ti51/to51 p26/ti52/to52 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p37/rtp7 p36/rtp6 p35/rtp5 p34/rtp4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
7 m pd78f0988 preliminary data sheet u12805ej1v0ds00 ad0 to ad7: address/data bus adtrg: ad trigger input ani0 to ani7: analog input astb: address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground intp0 to intp7: external interrupt input p00 to p03: port 0 p10 to p17: port 1 p20 to p26: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p64 to p67: port 6 rd: read strobe reset: reset rtp0 to rtp7: real-time port rxd00, rxd01: receive data sck: serial clock si: serial input so: serial output ti000, ti001, ti010, ti011, ti50 to ti52: timer input to00, to01, to50 to to52, to70 to to75: timer output toff7: timer output off txd00, txd01: transmit data v dd0 , v dd1 : power supply v pp : programming power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal
m pd78f0988 8 preliminary data sheet u12805ej1v0ds00 block diagram 8-bit timer/ event counter 50 8-bit timer/ event counter 51 8-bit timer/ event counter 52 watchdog timer a/d converter interrrupt control real-time output port to50/ti50/p24 ani0/p10 to ani7/p17 av dd av ss av ref intp1/p01 and intp2/p02 78k/0 cpu core flash memory (60 kbytes) ram (1024 bytes) v dd0 , v dd1 v ss0 , v ss1 v pp port 0 port 1 port 3 port 4 port 5 port 6 external access system control p00 to p03 p10 to p17 p30 to p37 port 2 p20 to p26 p40 to p47 p50 to p57 p64 to p67 ad0/p40 to ad7/p47 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 to51/ti51/p25 16-bit timer/ event counter 00 16-bit timer/ event counter 01 ti000/to00/intp4/p54 ti010/intp5/p55 ti011/intp7/p57 ti001/to01/intp6/p56 to52/ti52/p26 uart00 uart01 rtp0/p30 to rtp7/p37 txd00/p21 rxd00/p20 txd01/p23 rxd01/p22 sio3 sck/p51 si/p52 so/p53 intp0/toff7/p00 intp3/adtrg/p03 intp5/ti010/p55 intp6/ti001/to01/p56 intp4/ti000/to00/p54 intp7/ti011/p57 real-time pulse unit to70 to to75
m pd78f0988 9 preliminary data sheet u12805ej1v0ds00 contents 1. differences between m pd78f0988 and mask rom versions ...................................... 10 2. pin functions ................................................................................................................ ................ 11 2.1 port pins ............................................................................................................................... ..................... 11 2.2 non-port pins ............................................................................................................................... ............ 12 2.3 pin i/o circuits and recommended connection of unused pins .................................................... 14 3. internal memory size switching register (ims) ........................................................... 16 4. internal expansion ram size switching register (ixs) ............................................. 17 5. flash memory programming ................................................................................................. 18 5.1 selection of communication mode ....................................................................................................... 18 5.2 flash memory programming functions ............................................................................................... 19 5.3 connection of flashpro ii and flashpro iii .......................................................................................... 19 6. electrical specifications ...................................................................................................... 21 7. package drawings ..................................................................................................................... 36 appendix a. development tools ................................................................................................. 3 8 appendix b. related documents ................................................................................................ 40
m pd78f0988 10 preliminary data sheet u12805ej1v0ds00 1. differences between m pd78f0988 and mask rom versions the m pd78f0988 is a product with a flash memory which enables on-board writing, erasing and rewriting of programs. except for flash memory specifications, the same functions as those of mask rom versions can be obtained by setting the internal memory size switching register (ims) and internal expansion ram size switching register (ixs). table 1-1 shows the differences between the flash memory version ( m pd78f0988) and mask rom versions ( m pd780982, 780983, 780984, 780986, 780988). table 1-1. differences between m pd78f0988 and mask rom versions item m pd78f0988 mask rom versions internal rom structure flash memory mask rom internal rom capacities 60 kbytes m pd780982: 16 kbytes m pd780983: 24 kbytes m pd780984: 32 kbytes m pd780986: 48 kbytes m pd780988: 60 kbytes internal expansion ram capacities 1024 bytes m pd780982: none m pd780983: none m pd780984: none m pd780986: 1024 bytes m pd780988: 1024 bytes change of internal rom capacity with internal available note 1 not available memory size switching register (ims) change of internal expansion ram capacity with available note 2 not available internal expansion ram size switching register (ixs) test pin not provided provided v pp pin provided not provided notes 1. flash memory capacity becomes 60 kbytes by reset input. 2. internal expansion ram capacity becomes 0 byte by reset input. caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom versions.
m pd78f0988 11 preliminary data sheet u12805ej1v0ds00 2. pin functions 2.1 port pins pin name i/o function after reset alternate function p00 i/o port 0 input intp0/toff7 p01 4-bit i/o port intp1 p02 input/output can be specified in 1-bit units. intp2 p03 an on-chip pull-up resistor can be specified by means of intp3/adtrg software. p10 to p17 input port 1 input ani0 to ani7 8-bit input only port p20 i/o port 2 input rxd00 p21 7-bit i/o port txd00 p22 input/output can be specified in 1-bit units. rxd01 p23 an on-chip pull-up resistor can be specified by means of txd01 p24 software. ti50/to50 p25 ti51/to51 p26 ti52/to52 p30 to p37 i/o port 3 input rtp0 to rtp7 8-bit i/o port input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software. p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software. p50 i/o port 5 input ? p51 8-bit i/o port sck p52 input/output can be specified in 1-bit units. si p53 leds can be driven directly. so p54 an on-chip pull-up resistor can be specified by means of intp4/ti000/to00 p55 software. intp5/ti010 p56 intp6/ti001/to01 p57 intp7/ti011 p64 i/o port 6 input rd p65 4-bit i/o port wr p66 input/output can be specified in 1-bit units. wait p67 an on-chip pull-up resistor can be specified by means of astb software.
m pd78f0988 12 preliminary data sheet u12805ej1v0ds00 2.2 non-port pins (1/2) pin name i/o function after reset alternate function intp0 input external interrupt request input for which the valid edge input p00/toff7 intp1 (rising edge, falling edge, or both rising and falling input p01 intp2 edges) can be specified input p02 intp3 input p03/adtrg intp4 input p54/ti000/to00 intp5 input p55/ti010 intp6 input p56/ti001/to01 intp7 input p57/ti011 ti50 input external count clock input to 8-bit timer (tm50) input p24/to50 ti51 external count clock input to 8-bit timer (tm51) input p25/to51 ti52 external count clock input to 8-bit timer (tm52) input p26/to52 ti000 external count clock input to 16-bit timer (tm00) input p54/intp4/to00 capture trigger input to capture register (cr000, cr010) of 16-bit timer (tm00) ti010 capture trigger input to capture register (cr000) of 16-bit input p55/intp5 timer (tm00) ti001 external count clock input to 16-bit timer (tm01) input p56/intp6/to01 capture trigger input to capture register (cr001, cr011) of 16-bit timer (tm01) ti011 capture trigger input to capture register (cr001) of 16-bit input p57/intp7 timer (tm01) to50 output 8-bit timer (tm50) output input p24/ti50 to51 8-bit timer (tm51) output input p25/ti51 to52 8-bit timer (tm52) output input p26/ti52 to00 16-bit timer (tm00) output input p54/intp4/ti000 to01 16-bit timer (tm01) output input p56/intp6/ti001 rtp0 to rtp7 output real-time output port that outputs pulses in synchronization input p30 to p37 with trigger signals outputs from the real-time pulse unit txd00 output asynchronous serial interface serial data output input p21 txd01 input p23 rxd00 input asynchronous serial interface serial data input input p20 rxd01 input p22 sck i/o serial interface serial clock input/output input p51 si input serial interface serial data input input p52 so output serial interface serial data output input p53 ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input external trigger signal input to the a/d converter input p03/intp3 to70 to to75 output timer output for the 3-phase pwm inverter control hi-z e toff7 input timer output (to70 to to75) stop external input input p00/intp0 ad0 to ad7 i/o address/data bus for expanding memory externally input p40 to p47 rd output strobe signal output for reading from external memory input p64 wr strobe signal output for writing to external memory input p65 wait input wait insertion at external memory access input p66 astb output strobe output that externally latches address information input p67 output to ports 4 and 5 to access external memory av ref input a/d converter reference voltage input e e av dd e a/d converter analog power supply e e
m pd78f0988 13 preliminary data sheet u12805ej1v0ds00 2.2 non-port pins (2/2) pin name i/o function after reset alternate function av ss e a/d converter ground potential e e reset input system reset input e e x1 input connecting crystal resonator for system clock oscillation e e x2 e ee v dd0 e positive power supply for ports e e v ss0 e ground potential for ports e e v dd1 e positive power supply except for ports e e v ss1 e ground potential except for ports e e v pp e high-voltage application during program write/verify. e e in the normal operation mode, connect directly to v ss0 .
m pd78f0988 14 preliminary data sheet u12805ej1v0ds00 2.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 2-1. for the input/output circuit configuration of each type, refer to figure 2-1. table 2-1. types of pin input/output circuits pin name input/output i/o recommended connection of unused pins circuit type p00/intp0/toff7 8-c input/output independently connect to v ss0 via a resistor. p01/intp1 p02/intp2 p03/intp3/adtrg p10/ani0 to p17/ani7 25 input independently connect to v dd0 or v ss0 via a resistor. p20/rxd00 8-c input/output p21/txd00 5-h p22/rxd01 8-c p23/txd01 5-h p24/ti50/to50 8-c p25/ti51/to51 p26/ti52/to52 p30/rtp0 to p37/rtp7 5-h p40/ad0 to p47/ad7 p50 p51/sck 8-c p52/si 5-h p53/so p54/intp4/ti000/to00 p55/intp5/ti010 p56/intp6/ti001/to01 p57/intp7/ti011 p64/rd p65/wr p66/wait p67/astb to70 to to75 4 output leave open. reset 2 input e av dd e e connect to v dd0 . av ref connect to v ss0 . av ss v pp connect directly to v ss0 .
m pd78f0988 15 preliminary data sheet u12805ej1v0ds00 figure 2-1. pin input/output circuits type 2 schmitt-triggered input with hysteresis characteristics push-pull output that enables high-impedance output (both p-ch and n-ch are off) in type 4 data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pullup enable type 5-h v ss0 data output disable p-ch out v dd0 n-ch v ss0 data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pullup enable v ss0 type 8-c type 25 input enable comparator + p-ch n-ch v ref (threshold voltage) v ss0 in
m pd78f0988 16 preliminary data sheet u12805ej1v0ds00 7 6 5 4 3 2 1 0 address after reset r/w ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 fff0h cfh r/w rom3 rom2 rom1 rom0 selection of internal rom capacity 0 1 0 0 16 kbytes 0 1 1 0 24 kbytes 1 0 0 0 32 kbytes 1 1 0 0 48 kbytes 1 1 1 1 60 kbytes other than above setting prohibited ram2 ram1 ram0 selection of internal high-speed ram capacity 1 1 0 1024 bytes other than above setting prohibited 3. internal memory size switching register (ims) this register is set by software not to use a part of internal memory. the memory mapping can be made the same as that of mask rom versions with different types of internal memory capacity by setting ims. ims is set with an 8-bit memory manipulation instruction. ims is set to cfh by reset input. figure 3-1. format of internal memory size switching register table 3-1 shows the ims setting values to make the memory mapping the same as those of mask rom versions. table 3-1. setting value of internal memory size switching register target mask rom versions ims setting value m pd780982 c4h m pd780983 c6h m pd780984 c8h m pd780986 cch m pd780988 cfh
m pd78f0988 17 preliminary data sheet u12805ej1v0ds00 7 6 5 4 3 2 1 0 address after reset r/w 00 0 ixram4 ixram3 ixram2 i xram1 ixram0 fff4h 0ch r/w ixs ixram4ixram3 ixram2 ixram1 ixram0 selection of internal expansion ram capacity 0 1 0 1 0 1024 bytes 01 1 0 0 no internal expansion ram other than above setting prohibited 4. internal expansion ram size switching register (ixs) this register is used to set internal expansion ram capacity by software. the memory mapping can be made the same as that of mask rom versions with different types of internal expansion ram capacity by setting ixs. ixs is set with an 8-bit memory manipulation instruction. ixs is set to 0ch by reset input. figure 4-1. format of internal expansion ram size switching register table 4-1 shows the ixs setting values to make the memory mapping the same as those of mask rom versions. table 4-1. setting value of internal expansion ram size switching register target mask rom versions ixs setting value m pd780982 0ch m pd780983 m pd780984 m pd780986 0ah m pd780988
m pd78f0988 18 preliminary data sheet u12805ej1v0ds00 v pp reset 10 v v dd v ss v dd v ss 1 2 n v pp pulses flash memory write mode 5. flash memory programming on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is done after connecting a dedicated flash programmer (flashpro ii (part number fl-pr2), flashpro iii (part numbers fl-pr3 and pg-fp3)) to the host machine and target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to flashpro ii or flashpro iii. remark fl-pr2 and fl-pr3 are products of naito densei machida mfg. co., ltd. 5.1 selection of communication mode writing to flash memory is performed using flashpro ii and iii with a serial communication mode. select the communication mode for writing from table 5-1. for the selection of the communication mode, a format like the one shown in figure 5-1 is used. the communication modes are selected using the v pp pulse numbers shown in table 5-1. table 5-1. communication mode list communication mode number of pin used number of channels v pp pulses 3-wire serial i/o 1 sck/p51 0 si/p52 so/p53 uart 1 rxd00/p20 8 txd00/p21 pseudo 3-wire serial i/o 1 p24/ti50/to50 (serial data input) 12 mode note p25/ti51/to51 (serial data output) p26/ti52/to52 (serial clock input) note serial transfer is performed by controlling ports with software. caution always select the communication mode according to the number of v pp pulses shown in table 5- 1. figure 5-1. communication mode selection format
m pd78f0988 19 preliminary data sheet u12805ej1v0ds00 note for input to x1, not clk but a normal oscillator can also be used. 5.2 flash memory programming functions flash memory writing is performed through command and data transmit/receive operations using the selected communication mode. the main functions are listed in table 5-2. table 5-2. main functions of flash memory programming function description batch erase erases the contents of the entire memory. batch blank check checks that the entire memory has been deleted. data write performs writing to flash memory according to the write start address and the number of the data to be written (the number of bytes). batch verify compares the contents of the entire memory and the input data. 5.3 connection of flashpro ii and flashpro iii the connection of the flashpro ii, flashpro iii and the m pd78f0988 differs depending on the communication mode. each type of connection is shown in figures 5-2, 5-3, and 5-4, respectively. figure 5-2. connection of flashpro ii and flashpro iii using 3-wire serial i/o mode v pp v clk dd reset flashpro ii, iii sck sck so si gnd v pp v v ss0 x1 v v dd0 note dd1 reset si so ss1 pd78f0988 m
m pd78f0988 20 preliminary data sheet u12805ej1v0ds00 figure 5-3. connection of flashpro ii and flashpro iii using uart mode note for input to x1, not clk but a normal oscillator can also be used. figure 5-4. connection of flashpro ii and flashpro iii using pseudo 3-wire serial i/o mode note for input to x1, not clk but a normal oscillator can also be used. v v pp clk dd reset so si v ss v pp v x1 dd0 note v dd1 v ss1 v ss0 reset rxd00 txd00 pd78f0988 m flashpro ii, iii (serial data output) v v clk pp reset dd sck so si v ss v pp v x1 dd0 note v dd1 p25 v ss1 v ss0 reset pd78f0988 m flashpro ii, iii (serial clock input) (serial data input) p24 p26
m pd78f0988 21 preliminary data sheet u12805ej1v0ds00 6. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd e0.3 to +6.5 v v pp e0.3 to +10.5 v av dd e0.3 to v dd + 0.3 v av ref e0.3 to v dd + 0.3 v av ss e0.3 to +0.3 v input voltage v i p00 to p03, p10 to p17, p20 to p26, p30 to p37, p50 e0.3 to v dd + 0.3 v to p57, p64 to p67, to70 to to75, x1, x2, reset output voltage v o e0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss e 0.3 to av ref + 0.3 v and e0.3 to v dd + 0.3 output current, high i oh per pin e10 ma p00, p01, p30 to p37, p40 to p47, p50 to p57, p64 to p67 total e15 ma p02, p03, p20 to p26, to70 to to75 total e15 ma output current, low i ol note p00 to p03, p10 to p17, p20 to p26, peak value 20 ma p30 to p37, p40 to p47, p64 to p67 per pin rms value 10 ma p50 to p57, to70 to to75 per pin peak value 30 ma rms value 15 ma p00, p01, p30 to p37, p40 to p47, p64 to p67 peak value 50 ma total rms value 20 ma p02, p03, p20 to p26 total peak value 30 ma rms value 15 ma to70 to to75 total peak value 100 ma rms value 70 ma p50 to p57 total peak value 100 ma rms value 70 ma operating ambient t a e40 to +85 c temperature storage temperature t stg e40 to +125 c note the rms value should be calculated as follows: [rms value] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz unmeasured pins returned to 0 v 15 pf i/o capacitance c io f = 1 mhz p00 to p03, p20 to p26, p30 15 pf unmeasured pins to p37, p40 to p47, p50 to returned to 0 v p57, p64 to p67, to70 to to75 remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
m pd78f0988 22 preliminary data sheet u12805ej1v0ds00 system clock oscillator characteristics (t a = e40 to +85 c, v dd = 4.0 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 1.0 8.38 mhz resonator frequency (f x ) note 1 oscillation after v dd reaches 4 ms stabilization oscillation time note 2 voltage range min. crystal oscillation 1.0 8.38 mhz resonator frequency (f x ) note 1 oscillation after v dd reaches 10 ms stabilization oscillation time note 2 voltage range min. external clock x1 input frequency 1.0 8.38 mhz (f x ) note 1 x1 input high-/low- 50 500 ns level width (t xh , t xl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. c2 x1 x2 v pp c1 x2 x1 pd74hcu04 m c2 x1 x2 v pp c1
m pd78f0988 23 preliminary data sheet u12805ej1v0ds00 recommended oscillator constant system clock: ceramic resonator (t a = e40 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v ) murata mfg. csa2.00mg040 2.00 100 100 4.0 5.5 co., ltd. cst2.00mg040 2.00 on-chip on-chip 4.0 5.5 csa3.58mg 3.58 30 30 4.0 5.5 cst3.58mgw 3.58 on-chip on-chip 4.0 5.5 csa4.00mg 4.00 30 30 4.0 5.5 cst4.00mgw 4.00 on-chip on-chip 4.0 5.5 csa4.19mg 4.19 30 30 4.0 5.5 cst4.19mgw 4.19 on-chip on-chip 4.0 5.5 csa4.91mg 4.91 30 30 4.0 5.5 cst4.91mgw 4.91 on-chip on-chip 4.0 5.5 csa5.00mg 5.00 30 30 4.0 5.5 cst5.00mgw 5.00 on-chip on-chip 4.0 5.5 csa7.37mtz 7.37 30 30 4.0 5.5 cst7.37mtw 7.37 on-chip on-chip 4.0 5.5 csa8.00mtz 8.00 30 30 4.0 5.5 cst8.00mtw 8.00 on-chip on-chip 4.0 5.5 csa8.38mtz 8.38 30 30 4.0 5.5 cst8.38mtw 8.38 on-chip on-chip 4.0 5.5 csa10.0mtz 10.0 30 30 4.0 5.5 cst10.0mtw 10.0 on-chip on-chip 4.0 5.5 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
m pd78f0988 24 preliminary data sheet u12805ej1v0ds00 dc characteristics (t a = e40 to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p37, p40 to p47, p50, p53, 0.7v dd v dd v high p64 to p67 v ih2 reset, p00 to p03, p20, p22, p24 to p26, p51, p52, 0.8v dd v dd v p54 to p57 v ih3 x1, x2 v dd e 0.5 v dd v input voltage, low v il1 p10 to p17, p21, p23, p30 to p37, p40 to p47, p50, p53, 0 0.3v dd v p64 to p67 v il2 reset, p00 to p03, p20, p22, p24 to p26, p51, p52, 0 0.2v dd v p54 to p57 v il3 x1, x2 0 0.4 v output voltage, v oh1 4.5 v v dd 5.5 v, i oh = e1 ma v dd e 1.0 v dd v high i oh = e100 m a v dd e 0.5 v dd v output voltage, v ol1 p50 to p57, to70 to to75 5.0 v v dd 5.5 v, 0.4 2.0 v low i ol = 15 ma p00 to p03, p20 to p26, 5.0 v v dd 5.5 v, 0.4 v p30 to p37, p40 to p47, i ol = 1.6 ma p64 to p67 v ol2 i ol = 400 m a 0.5 v input leakage i lih1 v in = v dd p00 to p03, p10 to p17, 3 m a current, high p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67, to70 to to75, reset i lih2 x1, x2 20 m a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, e3 m a current, low p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67, to70 to to75, reset i lil2 x1, x2 e20 m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v e3 m a current, low software pull-up r 2 v in = 0 v 15 30 90 k w resistor p00 to p03, p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67 power supply i dd1 8.38-mhz crystal v dd = 5.0 v 10% note 2 when a/d 15 30 ma current note 1 oscillation converter operating mode stopped when a/d 16 32 ma converter operating i dd2 8.38-mhz crystal v dd = 5.0 v 10% note 2 when peripheral 1.3 2.6 ma oscillation halt function mode stopped when peripheral 7.3 ma function operating i dd3 stop mode v dd = 5.0 v 10% 0.1 30 m a notes 1. refers to the total current flowing to the internal power supply (v dd0 and v dd1 ). the peripheral operation current is included however, the current flowing to the pull-up resistor of ports and av ref pin is not included. 2. high-speed mode operation (when processor clock control register (pcc) is set to 00h). remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
m pd78f0988 25 preliminary data sheet u12805ej1v0ds00 ac characteristics (1) basic operation (t a = e40 to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with system clock 0.24 32 m s (min. instruction execution time) ti000, ti001, f ti0 0f x /64 mhz ti010, ti011 input frequency ti000, ti001, t tih0 2/f sam + m s ti010, ti011 t til0 0.1 note input high-/ low-level width ti50, ti51, ti52 f ti5 8-/16-bit precision 0 4 mhz input frequency ti50, ti51, ti52 t tih5 8-/16-bit precision 100 ns input high-/ t til5 low-level width interrupt request t inth intp0 to intp7 1 m s input high-/ t intl low-level width toff input t toffh 2 m s high-/low-level t toffl width reset input t rsl 10 m s low-level width note selection of f sam = f x , f x /4, f x /32 is possible with bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00) or with bits 0 and 1 (prm010, prm011) of prescaler mode register 01 (prm01). note that when selecting ti000 (tm00) or ti001 (tm01) valid edge as the count clock, f sam = f x /16.
m pd78f0988 26 preliminary data sheet u12805ej1v0ds00 t cy vs v dd (system clock operation) 5.0 1.0 2.0 0.24 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 32.0 10.0 guaranteed operation range m
m pd78f0988 27 preliminary data sheet u12805ej1v0ds00 (2) read/write operation (t a = e40 to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy e 54 ns t add2 (3 + 2n)t cy e 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy e 87 ns t rdd2 (3 + 2n)t cy e 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy e 33 ns t rdl2 (2.5 + 2n)t cy e 33 ns wait input time from rd t rdwt1 t cy e 43 ns t rdwt2 t cy e 43 ns wait input time from wr t wrwt 0.5t cy e 25 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl (1.5 + 2n)t cy e 15 ns rd delay time from astb t astrd 6ns wr delay time from astb t astwr 2t cy e 15 ns astb - delay time from rd - at external fetch t rdast 0.8t cy e 15 1.2t cy ns write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 10 60 ns rd - delay time from wait - t wtrd 0.8t cy 2.5t cy + 25 ns wr - delay time from wait - t wtwr 0.8t cy 2.5t cy + 25 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l is the load capacitance of ad0 to ad7, rd, wr, wait, and astb pins.)
m pd78f0988 28 preliminary data sheet u12805ej1v0ds00 (3) serial interface (t a = e40 to +85 c, v dd = 4.0 to 5.5 v) (a) 3-wire serial i/o mode (sck... internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 954 ns sck high-/low-level width t kh1 t kcy1 /2 e 50 ns t kl1 si setup time (to sck - )t sik1 100 ns si hold time (from sck - )t ksi1 400 ns so output delay time t kso1 c = 100 pf note 300 ns from sck note c is the load capacitance of the sck and so output lines. (b) 3-wire serial i/o mode (sck... external clock input) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 800 ns sck high-/low-level width t kh2 400 ns t kl2 si setup time (to sck - )t sik2 100 ns si hold time (from sck - )t ksi2 400 ns so output delay time t kso2 c = 100 pf note 300 ns from sck note c is the load capacitance of the sck and so output lines. (c) uart mode (uart00) (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 125000 bps (d) uart mode (uart00) (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 115200 bps bit rate allowable error 0.87 % output pulse width 1.2 0.24/fbr note m s input pulse width 4/f x m s note fbr: set baud rate (e) uart mode (uart01) (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 38400 bps
m pd78f0988 29 preliminary data sheet u12805ej1v0ds00 ac timing test points (excluding x1 input) clock timing ti timing toff timing x1 input v ih3 ( min. ) v il3 ( max. ) 1/f x t xl t xh ti000, ti001, ti010, ti011 ti50, ti51, ti52 1/f ti5 t til5 t tih5 1/f ti0 t til0 t tih0 toff7 t toffl t toffh 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd
m pd78f0988 30 preliminary data sheet u12805ej1v0ds00 read/write operation external fetch (no wait): external fetch (wait insertion): ad0 to ad7 astb rd 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad operation code t rdast t astrd t rdl1 t rdh ad0 to ad7 astb rd 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 operation code t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd
m pd78f0988 31 preliminary data sheet u12805ej1v0ds00 external data access (no wait): external data access (wait insertion): read data ad0 to ad7 astb rd wr hi-z hi-z 8-bit address write data t add2 t ads t asth t adh t rdad t rdd2 t rdh t astrd t rdl2 t wds t wdh t wrl t astwr t rdwd t wrwd read data hi-z hi-z 8-bit address write data t add2 t ads t asth t adh t rdad t rdd2 t rdh t astrd t rdl2 t wds t wdh t wrl t wtl t wtl t astwr t rdwd t rdwt2 t wrwd t wrwt t wtwr t wtrd ad0 to ad7 astb rd wr wait
m pd78f0988 32 preliminary data sheet u12805ej1v0ds00 serial transfer timing 3-wire serial i/o mode: m = 1, 2 si so t kcym t klm t khm t sikm t ksim input data t ksom output data sck
m pd78f0988 33 preliminary data sheet u12805ej1v0ds00 a/d converter characteristics (t a = e40 to +85 c, v dd = av dd = 4.0 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr conversion time t conv 4.0 v av ref 5.5 v 14 96 m s 2.7 v av ref < 4.0 v 19 96 m s zero-scale offset note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr full-scale offset note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr non-linearity error 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb differential non-linearity error 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ian 0av ref v reference voltage av ref 2.7 av dd v resistance between av ref r ref when a/d converter is not operating 20 40 k w and av ss note excludes quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. data memory stop mode low supply voltage data retention characteristics (t a = e40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 2.0 5.5 v supply voltage data retention i dddr v dddr = 2.0 v 0.1 10 m a power supply current release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts).
m pd78f0988 34 preliminary data sheet u12805ej1v0ds00 data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) intp0 to intp7 t intl t inth reset t rsl v dd stop instruction execution reset stop mode data retention mode v dddr internal reset operation halt mode operation mode t wait t srel interrupt request input timing reset input timing v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr halt mode operation mode t srel t wait
m pd78f0988 35 preliminary data sheet u12805ej1v0ds00 flash memory programming characteristics (v dd = 4.0 to 5.5 v, v ss = 0 v, v pp = 9.7 to 10.3 v) (1) basic characteristics parameter symbol conditions min. typ. max. unit operation frequency f x 1.0 8.38 mhz supply voltage v dd 4.0 5.5 v v ppl when v pp low-level is detected 0 0.2v dd v v pp when v pp high-level is detected 0.8v dd v dd 1.2v dd v v pph when v pp high-voltage is detected 9.0 10.0 10.5 v when programming 9.7 10.0 10.3 v v pp power supply current i pp v pp = 10.0 v 50 100 ma write time (per 1 byte) t wrt 50 500 m s number of rewrites c wrt 20 times erase time t erase 120s programming temperature t prg 10 40 c (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit v pp - set time from v dd - t drpsr v pp high voltage 0 m s reset - set time from v pp - t psrrf v pp high voltage 1.0 m s v pp count start time from reset - t rfcf v pp high voltage 1.0 m s count execution time t count 20 ms v pp counter high-level width t ch 8.0 m s v pp counter low-level width t cl 8.0 m s v pp counter noise elimination width t nfw 40 ns flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psrrf t drpsr t ch t cl t count
m pd78f0988 36 preliminary data sheet u12805ej1v0ds00 7. package drawings i j g h f d n m cb m r 64 33 32 1 k l notes 1. controlling dimension millimeter. p64c-70-750a,c-3 item millimeters inches b c d f g h j k 1.778 (t.p.) 3.2 0.3 0.51 min. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 0.2 n 0 to 15 0.50 0.10 0.9 min. r 0.070 max. 0.020 0.035 min. 0.126 0.012 0.020 min. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0 to 15 +0.004 ?.003 0.070 (t.p.) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil) 2. each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. 3. item "k" to center of leads when formed parallel. a 58.0 2.283 +0.028 ?.008 +0.68 ?.20 i 4.05 0.159 +0.011 ?.008 +0.26 ?.20 a +0.009 ?.008
m pd78f0988 37 preliminary data sheet u12805ej1v0ds00 64 pin plastic qfp ( 14) item millimeters inches i j 0.8 (t.p.) 0.15 0.006 0.031 (t.p.) a 17.6 0.4 0.693 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.6 0.4 0.693 0.016 f g 1.0 1.0 0.039 0.039 h 0.37 0.015 p64gc-80-ab8-4 l 0.8 0.2 0.031 +0.009 ?.008 m 0.17 0.007 n 0.10 0.004 +0.08 ?.07 +0.08 ?.07 q 0.1 0.1 0.004 0.004 r s 2.85 max. 5 5 5 5 0.113 max. +0.003 ?.004 note 1. controlling dimension millimeter. 2. each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. m q r k m l p g f hi s detail of lead end k 1.8 0.2 0.071 0.008 p 2.55 0.1 0.100 0.004 +0.003 ?.004 48 49 32 64 1 17 16 33 s a b cd j ns
m pd78f0988 38 preliminary data sheet u12805ej1v0ds00 appendix a. development tools the following development tools are available for system development using the m pd780988 subseries. also refer to (5) cautions on using development tools . (1) language processing software ra78k/0 assembler package common to 78k/0 series cc78k/0 c compiler package common to 78k/0 series df780988 device file for m pd780988 subseries cc78k/0-l c compiler library source file common to 78k/0 series (2) flash memory writing tools flashpro ii (part no. fl-pr2), flash programmer dedicated to on-chip flash memory microcontroller flashpro iii (part no. fl-pr3, pg-fp3) fa-64cw adapter for flash memory writing fa-64gc (3) debugging tools when ie-78k0-ns in-circuit emulator is used ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa note performance board for enhancement and expansion of ie-78k0-ns function ie-70000-98-if-c interface adapter when pc-9800 series pc (except notebook type) is used as host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable when notebook pc is used as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when using ibm pc/at tm or compatible as host machine (isa bus supported) ie-70000-pci-if adapter necessary when using pci bus incorporated personal computer as host machine ie-780988-ns-em4 emulation board to emulate m pd780988 subseries ie-78k0-ns-p01 i/o board necessary to emulate m pd780988 subseries np-64cw emulation probe for 64-pin plastic shrink dip (cw type) np-64gc emulation probe for 64-pin plastic qfp (gc-ab8 type) np-64gc-tq ev-9200gc-64 conversion socket to connect the np-64gc and a target system board on which the 64-pin plastic qfp (gc-ab8 type) can be mounted tgc-064sap conversion adapter to connect the np-64gc-tq and a target system board on which the 64-pin plastic qfp (gc-ab8 type) can be mounted id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df780988 device file for m pd780988 subseries note under development
m pd78f0988 39 preliminary data sheet u12805ej1v0ds00 when ie-78001-r-a in-circuit emulator is used ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter when pc-9800 series pc (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at or compatible as host machine (isa bus supported) ie-70000-pci-if adapter necessary when using pci bus incorporated personal computer as host machine ie-78000-r-sv3 interface adapter and cable when using ews as host machine ie-780988-ns-em4 emulation board to emulate m pd780988 subseries ie-78k0-ns-p01 i/o board necessary to emulate m pd780988 subseries ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-780988-ns-em4 and ie-78k0-ns-p01 on ie-78001-r-a ep-78240cw-r emulation probe for 64-pin plastic shrink dip (cw type) ep-78240gc-r emulation probe for 64-pin plastic qfp (gc-ab8 type) ev-9200gc-64 socket to be mounted on a target system board made for 64-pin plastic qfp (gc-ab8 type) id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780988 device file for m pd780988 subseries (4) real-time os rx78k/0 real-time os for 78k/0 series mx78k0 os for 78k/0 series (5) cautions on using development tools the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780988. the cc78k/0 and rx78k/0 are used in combination with the ra78k/0 or df780988. the fl-pr2, fl-pr3, fa-64cw, fa-64gc, np-64cw, np-64gc, and np-64gc-tq are products made by naito densei machida mfg. co., ltd. (tel +81-44-822-3813). contact an nec distributor regarding the purchase of these products. the tgc-064sap is a product made by tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) for third-party development tools, see the 78k/0 series selection guide (u11126e) . the host machine and os suitable for each software are as follows. host machine pc ews [os] pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k/0 ? note ? cc78k/0 ? note ? id78k0-ns ? e id78k0 ?? sm78k0 ? e rx78k/0 ? note ? mx78k0 ? note ? note dos-based software
m pd78f0988 40 preliminary data sheet u12805ej1v0ds00 appendix b. related documents documents related to devices document name document no. english japanese m pd780988 subseries user?s manual u13029e u13029j m pd780982, 780983, 780984, 780986, 780988 data sheet u12804e u12804j m pd78f0988 data sheet this manual u12805j m pd780988 subseries inverter control application note u13119e u13119j m pd780988 subseries special function register table e u12806j 78k/0 series instructions user?s manual u12326e u12326j 78k/0 series instruction table e u10903j 78k/0 series instruction set e u10904j documents related to development tools (user?s manuals) document name document no. english japanese ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly language u11789e u11789j ra78k series structured assembler preprocessor eeu-1402 u12323j cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k0 c compiler application note programming know-how u13034e u13034j ie-78k0-ns to be prepared to be prepared ie-78001-r-a to be prepared to be prepared ie-780988-ns-em4 to be prepared to be prepared ep-78240 u10332e eeu-986 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specifications i d78k0-ns integrated debugger windows based reference u12900e u12900j id78k0 integrated debugger ews based reference e u11151j id78k0 integrated debugger pc based reference u11539e u11539j id78k0 integrated debugger windows based guide u11649e u11649j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
m pd78f0988 41 preliminary data sheet u12805ej1v0ds00 documents related to embedded software (user?s manuals) document name document no. english japanese 78k/0 series real-time os fundamental u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 fundamental u12257e u12257j other related documents document name document no. english japanese semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to microcomputer-related products by third party e u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
m pd78f0988 42 preliminary data sheet u12805ej1v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd78f0988 43 preliminary data sheet u12805ej1v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m pd78f0988 the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98. 8 fip and iebus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such.

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